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Low-cost Additive Manufacturing Technique for Fabricating Through-Substrate Vias based three-dimensional micro-structures used in MEMS Applications

Primary Information

Domain

Manufacturing

Project No.

7510

Sanction and Project Initiation

Sanction No: F.No.:3-18/2015-TS-TS-1, DSIR/PACE/TDD-IMPRINT/751

Sanction Date: 29/11/2016

Project Initiation date: 14/03/2017

Project Duration: 36

Partner Ministry/Agency/Industry

Department of Scientific and Industrial Research

Role of partner:To provide technical and financial support in the project and to help the commercialization of any research outcome of this project

Support from partner:DSIR has arranged a project review meeting at New Delhi.and provided valuable feedback about the project

Principal Investigator

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Pradeep Dixit
Indian Institute of Technology Bombay, Mumbai

Host Institute

Co-PIs

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Suhas S Joshi
Indian Institute of Technology Bombay, Mumbai

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S. Usha
Central Manufacturing Technology Institute (CMTI), Bengaluru

Scope and Objectives

1. To develop a low cost micromachining technique to create micro-features in non-conductive materials such as glass
2. To demonstrate void-free copper filling in the etched holes and to use them in 3D Interconnect applications.

Deliverables

1. Electrochemical-discharge micromachining process for semiconductor hard-to-machine-materials such as glass
2. void-free metal-filled vias formed by electrodeposition

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Scientific Output

In this project, simultaneous formation of multiple through-holes in hard-to-machine brittle materials such as fused silica, will be demonstrated. Compared to conventional plasma etching, this process will have faster etch rate and lower cost.

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Results and outcome till date

A table top ECDM setup is ready which is able to create multiple holes in a 400 micrometer thick fused silica substrate in less than 10 min.

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Societal benefit and impact anticipated

Next steps

Filling of the etched holes by copper electrodeposition will be performed. To achieve this, a thin layer of conductive seed layer will be deposited.

Publications and reports

Manuscript submitted to Journal of Material processing Technology. The research outcome has been presented in 8th IEEE-INEC, Malaysia (Invited oral presentation), January 2018.

Patents

Scholars and Project Staff

Aftab Ahmed - Junior research fellow - 10.7.2017 to 14.05.2018
Saleem Khan - Research Associate - 15.06.2017 to 29.12.2017
Swati Rastogi - Project Research assistant -18.04.2017 to 12.07.2017
Swati Rastogi - PhD student - 12.07.2017 to 12.07.2018

Challenges faced

Due to the brittle nature of glass and low thickness ( 400 micrometer), samples are being cracked during the experimental processing. Due to the rough sidewalls, the deposition of continuous 300 nm thin seed layer by sputtering process has not been successful yet. Purchase activities have been affected due to ERP implementation at IIT Bombay.

Financial Information

  • Total sanction: Rs. 14538000

  • Amount received: Rs. 9189000

  • Amount utilised for Equipment: Rs. 1905807

  • Amount utilised for Manpower: Rs. 398677

  • Amount utilised for Consumables: Rs. 102506

  • Amount utilised for Contingency: Rs. 10000

  • Amount utilised for Travel: Rs. 11772

  • Amount utilised for Other Expenses: 0

  • Amount utilised for Overheads: Rs. 1531334

Equipment and facilities

High Voltage HIgh current pulse Power supply, computer operated XYZ table with motion controller, Table top polisher Opto-digital microscope (in process) Environmental chamber (in process) Facilities created: A table top Electrochemical discharge micro machining facility was developed, which is able to create micro-size features in non-conductive materials like fused silica.