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Development of Scalable GaN-based Distributed Dynamic Power Management System for IoT Applications with On-Demand Dynamic Thermal Management

Primary Information

Domain

Information & Communication Technology

Project No.

7188

Sanction and Project Initiation

Sanction No: F. No.: 3-18/2015-T.S.-I(Vol.III)

Sanction Date: 22/03/2017

Project Initiation date: 18/04/2017

Project Duration: 36

Partner Ministry/Agency/Industry

Ministry of Electronics and Information Technology (MEITY) and GE

 

Role of partner:MEITY is the partner financial agency, which is supposed to provide 50% of fund. GE has no financial role.

 

Support from partner:Not yet received any financial assistance from MEITY.

Principal Investigator

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Santanu Kapat
Indian Institute of Technology Kharagpur

Host Institute

Co-PIs

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Anandaroop Bhattacharya
Indian Institute of Technology Kharagpur

 

Scope and Objectives

This proposal is aimed to introduce scalable GaN based distributed DPM architectures with smart thermal solutions for IoT applications. The main objectives are to develop High frequency SMPS topologies with ultrafast DVS compatibility Scalable digital control for fast transient response, high energy efficiency, and reduced EMI problems Coordinated control with optimal task sequencing and digital external user interface Power and thermal models to characterize cooling requirements On demand cooling solutions with enhanced heat dissipation to maintain device temperature under prescribed limits a scalable dynamic power and thermal codesign framework prototype test systems for pilot demonstration

Deliverables

The proposed dynamic power and thermal codesign framework has the promise to offer a differentiable DPM architecture for powering industrial IoTs with the unique features of scalability, high power density with ultrafast DVS compatibility, high efficiency, scalable high performance digital control with optimal task sequencing, and smart thermal solutions under varying ambient temperature. The deliverables are as follows High frequency SMPS topologies to support direct input interface with the 48V DC bus, to power various IoT devices with voltage levels ranging from 1V to 24V, and to offer ultrafast DVS compatibility with reduced time and energy overheads Scalable digital control with fast response, high efficiency, and reduced EMI problems MATLAB system level simulation and PLECS circuit simulation Schematic and layout of the power and signal conditioning circuits PCB fabrication, component mounting, and development of prototype test bed Verilog HDL coding and closed loop hardware testing and verification Formulation of power and thermal models Understanding thermal aspects and cooling requirements Development of on demand dynamic thermal management system Developing intellectual properties and filing international patents Publications in the leading journals and conference proceedings Discussion with the industry mentor GE for commercialization

 

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Scientific Output

A high frequency novel DVS architecture for powering multi core processors and IoT devices is developed and a laboratory prototype is made with 12 V to 5 V input voltage and 0.6 V to 3.3 V output voltage levels. Experimentation is also done. This work is currently under documentation and we would soon be communicating to IEEE Transactions in Power Electronics. A two stage cascaded buck converter with 48 V to 3.3 V prototypes has been made and is successfully verified experimentally. A Novel 48 V to 1 V two stage architecture is developed for improving the transient response and increasing the light load efficiency. Experimentation is also done. A new hardware prototype was made for the same using the GaN FETs and the experimental investigation for this new board is currently underway. A Novel PID tuning mechanism for multi phase buck converters was developed for fast load and reference transient response. This was experimentally verified. A stabilizing digital controller was proposed to mitigate the constant power load induced instability in two stage architecture with 48 V to 3.3 V and also simultaneously achieves fast transient recovery and high energy efficiency. This method was experimentally verified. A Novel ripple based control is being developed to mitigate the constant power load induced instability in a two-stage 48 V to 3.3 V architecture with reduced resources and high efficiency. This is experimentally verified in the laboratory. This work is about to be communicated in IEEE Transactions in Power Electronics. It is interesting to observe the behaviour of cascaded converters while in operation. Thus, simulation based study is being carried out so far to analyse the performance, how the stability is affected by their interconnection and also efficiency. A single PoL converter was considered. Multiple PoLs are being connected and it is in progress. This requires coordinated digital control with optimal task sequencing. Numerical model of cooling impact of piezoelectric fans under mean flow has been completed using ANSYS workbench. This is a complex problem involving fluid-structure interaction.

 

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Results and outcome till date

1 High frequency SMPS topologies with ultra fast DVS compatibility is already identified
2 Scalable digital control for fast transient response, high energy efficiency, and reduced EMI problems is already developed
3 Coordinated control with optimal task sequencing and digital external user interface is in progress
4 power and thermal models to characterize cooling requirements is theoretical and numerical modeling completed
5 on demand cooling solutions with enhanced heat dissipation to maintain device temperature under prescribed limits and technology identified
6 a scalable dynamic power and thermal codesign framework is currently progress underway
7 Prototype test systems for pilot demonstration and New DC DC converters architectures are identified and preliminary experimental prototypes using MOSFETs have been developed. Experimental prototypes using GaN FETs have already been made and the hardware implementation in the laboratory is underway. Some of the pictures of the experimental prototypes are included in the subsequent sections.

The Major achievements during the course of the work are
1 Ultrafast DVS in breaking the conflicting design criteria for improvement of both load and reference transient
2 Fast Transient response for Two stage multiphase converter Proposed topology with switching capacitor arrangement allows instantaneous voltage transition to achieve extremely fast transient response.
3 Discrete time modelling of both Current and voltage fed isolated Dual Active Bridge converters has been developed for accurately capturing dynamic as well as steady state behaviour
4 Near optimal controller tuning in cascaded DC DC converter.
5 Discrete time framework for modeling of digitally controlled interconnected distributed DC architectures
6 Mixed signal average hysteresis control for a non inverting buck boost converter for fast envelope tracking power amplifiers

 

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Societal benefit and impact anticipated

This technology will be useful for almost all applications, including industrial, automotive, consumer electronics, communication, data processing, medical electronics, and many more, that would require IoT platform as next generation digitization. Some of the leading industries include GE, Intel, Texas Instruments, Samsung, ST microelectronics, Infineon, ON semiconductor, Qualcomm, Broadcom, NXP semiconductor, Cisco, to name a few. The thermal solutions and modeling framework can also be adopted by vendors like Aavid, Fujikura as well as ODMs like Compal, Quanta, Inventec and MEI Panasonic.

Next steps

New DC DC converters architectures are identified and preliminary experimental prototypes using MOSFETs have been developed. Experimental prototypes using GaN FETs have already been made and the hardware implementation in the laboratory is underway. Some of the pictures of the experimental prototypes are included in the subsequent sections. For pilot demonstration particularly including the on demand thermal management with casing, the fund from the partner ministry remains essential.

Publications and reports

Conference papers
1) A. Pal and S. Kapat, Accurate Discrete-Time Modeling of an Interleaved Current Fed Dual Active Bridge DC-DC Converter, Accepted for presentation in IEEE APEC, Anaheim, California, Mar. 2019.
2) A. Pal and S. Kapat, Discrete Time Modeling of a Naturally Commutated Current Fed Dual Active Bridge DC-DC Converter, Accepted for presentation in IEEE APEC, Anaheim, California, Mar. 2019.
3) A. Acharya, V. I. Kumar, and S. Kapat, Dynamic Bus Voltage Configuration in a Two-Stage Multi-Phase Buck Converter to mitigate transients, Accepted for presentation in IEEE APEC, Anaheim, California, Mar. 2019.
4) R. Roy and S. Kapat, Near Time Optimal Recovery in a Digitally Current Mode Controlled Buck Converter Driving a CPL, in IEEE APEC, San Antonio, Texas, USA, March 2018.

Journals papers
1) V. I. Kumar and S. Kapat, High Performance Mixed-Signal Hysteretic Average Current Controller Design for Envelope Tracking using a Non Inverting Buck Boost Converter, under revision, IEEE Trans. Power Electron., 2018.

Patents

1) V. I. Kumar and S. Kapat, A Dynamic Voltage Scaling Enabled per Cluster/Core Ultra-Fast Power Supply System for Multi-Core Processors, complete specification filed with App. No. 201731032852.
2) R. Roy, V. I. Kumar, and S. Kapat, A Novel Control Technique for Mitigating the Limit Cycle Oscillations in Intermediate Bus Architecture, complete specification filed with App. No. 201831038708.
3) A. Acharya, V. I. Kumar and S. Kapat, Dynamic Bus Voltage Configuration in a Two-Stage Multi-Phase Buck Converter to Mitigate Transients, currently under review at IIT Kharagpur.

Scholars and Project Staff

The following students are appointed Avishek Pal under SRF up to 31st March 2020 Arnab Acharya under JRF up to 31st March 2020 V. Inder Kumar under SRF up to 31st March 2020

Challenges faced

Due to unavailability of fund from the partner ministry, we are unable to build full scale hardware development .

Financial Information

  • Total sanction: Rs. 24480000

  • Amount received: Rs. 9431000

  • Amount utilised for Equipment: Rs. 1947992.82

  • Amount utilised for Manpower: Rs. 772333

  • Amount utilised for Consumables: Rs. 297610

  • Amount utilised for Contingency: Rs. 742592.32

  • Amount utilised for Travel: Rs. 5923

  • Amount utilised for Other Expenses: 663891

  • Amount utilised for Overheads: Rs. 1571834

Equipment and facilities

 

Manual triple channel DC power supply 2231A 30 3 Programmable DC power supply 80V, 40.5A, 1080W 2260B 80 40 Power supply 600V, 5.5A, 3300W N8742A Programmable AC and DC electronic load 63802 Isolated Oscilloscope with probes 200 MHz A test bed is created for dynamic power management.