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Development of Gallium-nitride HEMT Based Power Electronic Interfaces Enabled by Device-to-System Characterization and Modeling

Primary Information

Domain

Nano-Technology Hardware

Project No.

7057

Sanction and Project Initiation

Sanction No: F.No. 3-18/2015-T.S.-I(Vol. III)

Sanction Date: 21/03/2017

Project Initiation date:05/09/2017

Project Duration: 36

Partner Ministry/Agency/Industry

DST

Role of partner:NA

Support from partner:NA

Principal Investigator

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Swaroop Ganguly
IIT Bombay

Host Institute

Co-PIs

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Apurba Laha
IIT Bombay

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Dipankar Saha
IIT Bombay

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B. G. Fernandes
IIT Bombay

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Kishore Chatterjee
IIT Bombay

Scope and Objectives

Our first aim is to develop a technology platform wherein high-power GaN-HEMT devices will be characterized at IIT Bombay, models for these developed, and employed for the design of power electronic interfaces. Our second aim, following from the first, is to design and fabricate a prototype of a 600V DC-DC power converter for solar PV applications based on GaN-HEMT. Our goal beyond this project would be to commercialize GaN-HEMT based power-switching solutions for green energy applications through a start-up. This is envisaged to develop an end-to-end technology platform including device fabrication (which is being developed separately, and not as part of this project). In this case, the most promising commercial prospect for GaN-HEMT based power management solutions in India might turn out to be strategic electronics, which would have an enduring indigenization mandate. A corollary, if not an explicit goal, would be to establish sustained collaboration between the semiconductor device and power electronics communities.

Deliverables

The specifications for the final deliverable, viz. off-grid PV system with battery storage, will be as follows: a) Inverter Power rating 230 V, 300 W peak, 250 W nominal, 50 Hz b) PV panel 12 V, 350 W c) VRLA Battery 12 V, 100 Ah d) Switching frequency 500 kHz e) Device switch rating 600 V, Current rating 40 A f) Device case temperature 120 Degrees g) Efficiency > 95% h) Two stage system with DC-DC converter for MPPT charge controller, battery charging and Inverter i) High frequency transformer for compact design j) Natural cooling without using heat sink

Scientific Output

This is meant to be a technology development project. The output is a prototype converter for technology demonstration. The outcomes are: tightly collaborating semiconductor technology and power electronics R&D groups, working on nationally important missions like renewable energy and electric mobility; and, academia-industry collaboration.

Results and outcome till date

In Device-to-System modelling, we have developed a methodology that would allow us to take a new device, captured through its simulation or experimental characterization data; and incorporate it into the system simulator SABER, which is the standard platform for power electronic interface design. While this exercise is quite familiar for SPICE-like circuit simulators, it is nontrivial for SABER, which uses proprietary behavioural models for its components. The methodology that we have developed has been communicated to EDTM, a premier IEEE device conference. This is illustrated with the example of a novel GaN based transistor structure (junctionless FinFET) proposed in the literature. The devices that we have procured so far, their respective sources, and status are listed below. (1) GaN Systems (lateral, GaN on Si): Obtained through collaboration with VAJRA faculty, Prof. Shankar Madathil; system simulated in SPICE; measured at low voltage/current. (2) Tagore Technology (lateral GaN on Si): Talks ongoing with CEO, ex-IITB faculty, Dr. Amitava Das. (3) POWDEC (polarization superjunction - novel device concept): Obtained through collaboration with VAJRA faculty, Prof. Shankar Madathil; measured at low voltage/current - these samples not practically usable. (4) IITB internal (lateral GaN on Si): Heterostructures obtained from a third-party vendor via collaboration with Semi-Conductor Lab (SCL), Chandigarh, Department of Space. Devices were fabricated and characterized at IITB. The two main dimensions of converter design are: topology selection, and component selection. The following points pertaining to these have been considered here. 1) Topology selection: Choice is based on power rating, output voltage, and application; topologies may be non-isolated (e.g. buck, boost, cuk, SEPIC), or isolated (e.g. fly-back, forward, push-pull, full-bridge). 2) Component selection a. Switch: MOSFET/diode etc. Depends on voltage and power rating. b. Filter inductor size: Depends on allowable ripple current, usually 10-15% of load current c. Filter capacitor size: Depends on allowable output voltage ripple, usually 5% of output voltage. The starting point for the converter design is the GaN Systems device GS66508P, rated at 650V, 30A. The first step is a validation, viz. a comparison of the SPICE model and the data sheet. The SPICE model was then used to design the synchronous buck converter. A Double Pulse Test was also simulated to investigate the turn-off and turn-on power losses. At 200V, 20A and at 64V, 30A. The turn-off and turn-on transients for measurement of power loss is seen to be very small compared to silicon MOSFETs. While the data sheet and SPICE models are consistent and seem to portend excellent device characteristics, experimental characterization introduces some surprises. We were only able to carry out low voltage/current characterization for reasons that will be detailed later. A representative data set from a number of identical GaN Systems GS66508P 650V, 30A devices shows huge variability; indicating that variability and reliability might be the biggest concerns, and therefore test metrics, for this technology. This also indicates that there could be value in indigenous development of the device technology, so as to allow greater control over these aspects. We are pursuing a collaboration with the Semi-Conductor Lab (SCL, under Department of Space) in Chandigarh on GaN Power-HEMT technology to provide a possible scale-up path. As a first step, devices were fabricated and characterized on III-N on Si heterostructures procured by SCL. While device fabrication is outside the scope of this project, this activity is supported by other sources and provides us a potential internal source for devices. Tests to assess its quality were performed at IITB: atomic force microscopy (AFM), followed by fast-turnaround circular HEMT devices. Multi-fingered gate structure devices have also been fabricated at IITB, to realize high currents.

Societal benefit and impact anticipated

Wide-bandgap devices, among them GaN-HEMT, are poised to disrupt the field of power devices - which are key components for systems used in renewable energy and electric vehicles. They bring unprecedented energy efficiency, which has obvious sustainability benefits.

Next steps

1. Procure equipment
2. Perform high voltage/current characterization
3. Characterize devices
4. Incorporate in converter
5. Outreach to industry (started with high-profile academia-industry-government event on electric mobility))

Publications and reports

NA

Patents

NA

Scholars and Project Staff

International Faculty Collaborator (1): Prof. Shankar Madathil from the University of Sheffield, through the SERB VAJRA program. His contacts to the industry have been helpful. Postdoctoral Technologist (1): Dr. Joydeep Ghosh joined after his PhD from TU Vienna, one of the top Modelling and Simulation groups in the world, from where the standard device simulator MiniMOS originated. He is supported partially from the Institute and partially through this project. Ph.D. students (4): Working on device modelling, simulation, characterization, and power electronics. Two are supported from this project, and two from the Institute.

Challenges faced

1. ERP migration at IIT Bombay causing unprecedented delays in procurement.

Other information

We have reached out to electric vehicle manufacturers (from 2 wheelers to cars to trucks) for collaboration on power electronics. This was through an academia-industry conclave on electric mobility through the IIT Bombay Research Park.

Financial Information

  • Total sanction: Rs. 39000000

  • Amount received: Rs. 19693000

  • Amount utilised for Equipment: Rs. 0

  • Amount utilised for Manpower: Rs. 1564222

  • Amount utilised for Consumables: Rs. 0

  • Amount utilised for Contingency: Rs. 19160

  • Amount utilised for Travel: Rs. 211834

  • Amount utilised for Other Expenses: 0

  • Amount utilised for Overheads: Rs. 3553000

Equipment and facilities

There was only one (1) piece of crucial equipment (for high current/voltage measurement) that is budgeted. We have made progress towards the project goals without it. These include advances in device modeling, converter design, limited device procurement, and limited (low current/voltage measurements). The absence of the high current/voltage characterization setup does leave us with a major gap. The delay in procurement has a two-fold genesis. 1. The first delay of about 5 months (Apr to Sep, 2017) arose because the DST half of the equipment budget came through, but the MHRD half did not at the same time. 2. By the time it did, IIT Bombay had started its benighted ERP transition. This was to be one of the first import purchases from multiple funding sources under the new system; and faced difficulties in our system that have still not been surmounted after almost a year. It does seem close now though.