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Power Aware Compiler for Embedded Processors

Primary Information


Information & Communication Technology

Project No.


Sanction and Project Initiation

Sanction No: F.No. 3-18/2015-T.S.-I(Vol.III)

Sanction Date: 24/04/2017

Project Initiation date: 19/08/2017

Project Duration: 24

Partner Ministry/Agency/Industry

PI Institute


Role of partner:1. To provide 50% financial support in implementing the project. 2. to provide logistic and infrastructural support for the project implementation 3. Help the PI to reach out to the industry


Support from partner:1. Provide man power support in terms of providing salary two PhD scholars working in the project for two years - amounting 12.72 lakhs 2. Support in purchase of equipments worth of 9 lakhs maximum

Principal Investigator

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Dr. Bibhas Ghoshal
Indian Institute of Information Technology Allahabad

Host Institute


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Professor Indranil Sengupta
Indian Institute of Technology Kharagpur


Scope and Objectives

1) Exploring the state-of-art compiler optimization techniques for performance and study their effect on power consumption on high performance computing systems. 2) Exploring different compiler optimization techniques on state-of-art embedded processors, digital signal processors and high performance computing systems involving multi core architectures from power consumption perspective and study their effect on performance. Additionally, the techniques would be verified for their benefits by implementing them on different target systems for a set of representative benchmarks 3) Develop low power compiler techniques as patches for compilers of embedded systems 4) Develop a power aware compiler based on the LLVM compiler infrastructure framework.


1) Exploring different power aware compilation techniques for embedded and high perfor- mance computing systems (involving multi-core architecture) and to study the effect of these techniques on the performance of these systems. 2) Development of these power aware optimization techniques as patches for embedded com- pilers. A collection of such power aware optimization compiler patches will be provided as library which can be integrated in any compilation flow. These patches will allow the user of the embedded system to choose a compiler optimization technique suitable for a target application. 3) Validation of each of the power aware compilation technique by actual power measurements of different components when implemented on different target boards. The boards targeted for implementation will include (a) micro controller boards such as ARM boards supporting GCC/LLVM flow, (b) DSP boards (c) FPGA platforms 4) Integration of the proposed mechanisms in the LLVM compiler infrastructure framework 5) A Power aware compiler based on the LLVM infrastructure framework 6) In addition to the power aware compilation techniques, we would also explore thermal aware compilation techniques for embedded processors and evaluate their effect on the same target boards.


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Scientific Output



Results and outcome till date

1. Evaluated the impact of standard compiler pass sequences ( phase orders) provided by the -OX flags in the context of a Clang LLVM compiler targeting a multi core ARM processor in an ODROID XU4 board - embedded platform consisting of Exynos SoC ( used in Samsung Galaxy S4 smart phones) Exynos 5410 SoC includes a Cortex-A15 1.6GHz quad core CPU and 1.2 GHz Cortex-A7 quad core CPU : ARM Big.little architecture ( big) ARM A15 cores designed for performance and the ( little) ARM A7 cores designed for low power. Both the type of cores execute a task in turns so that the computation can be made more power efficient. Results : We identified for each benchmark,the optimisation levels that lead to the lowest power consumption and best performance Inferences drawn :Memory-intensive applications prefer lower performance optimization levels(O0/O1) while running on high performance cores(ARM A-15 cores) In contrast to the Memory-intensive applications, CPU-intensive applications prefer higher optimization levels (Os/O-f) while running on high performance cores. 2. Evaluated the impact of standard compiler pass sequences provided by the -OX flags in the context of a Clang LLVM compiler targeting a High performance computing system ( Workstation with two Intel Xeon E5-2630V4 CPU representing super computer node)


Societal benefit and impact anticipated

1. Low power software improves life time of system which brings down its cost - a major factor in consumer electronics 2. Computers and computing devices are everywhere. They have become part of our everyday life. However, these devices are also a source of harmful and toxic emissions which have ill effect on our health. Low power consumption promotes green computing which tries to reduce environment footprints of computers and other computing devices making them more energy efficient.

Next steps

Manually devising compiler phase ordering requires knowledge about code features, target architecture and compiler passes interdependence. Compilers have number of compiler passes making it a difficult problem Solution : use of machile learning methods for compiler autotuning Optimization Space problem Phase ordering problem Training : Training set -> Optimization design of expt. -> Compiler -> measurement collection -> ML algo -> Predictive model Training : Feature extraction -> Dimension reduction-> ML algo -> Predictive model Test : Feature extraction -> Dimension reduction -> ML algo -> Predictive model -> Predicted outcome Developing intermediate optimization passes for the LLVM

Publications and reports

The work done so far has been drafted into two articles and are ready to be submitted to a premier conference for review



Scholars and Project Staff

Two PhD students have been recruited who are currently working on the project. 1. Akash Sachan 2. Rakesh Kumar The students have been working on the project since August 2017 and would work for two years in the project. These students have also enrolled themselves in the regular PhD program of IIIT Allahabad so that the problems they have have been working on through this project will be their PhD problem as well and the scientific outputs in the form of publications would be part of their thesis.

Challenges faced

1. Lack of industry exposure : Since the basic intent of the project was to develop a product in collaboration with an industry partner, the lack of it is demeaning its utility. Companies such as Samsung, Intel, ARM, IBM and NVIDIA have been researching on this topic and would like to have innovative solutions for such problems. However, as PI of the project we do not have an existing framework to reach to these companies and it is still relying on personal contacts which in many cases do not work out.

Financial Information

  • Total sanction: Rs. 40.46 lakhs

  • Amount received: Rs. 20.23 lakhs

  • Amount utilised for Equipment: Rs. 4.42 lakhs

  • Amount utilised for Manpower: Rs. 7.90 lakhs

  • Amount utilised for Consumables: Rs. 0.53 lakhs

  • Amount utilised for Contingency: Rs. 0.03 lakhs

  • Amount utilised for Travel: Rs. 0.5 lakhs

  • Amount utilised for Other Expenses: 0

  • Amount utilised for Overheads: Rs. 0

Equipment and facilities


1. Workstation-Tyrone Camarero DS300TR-34 - 1 No. 2. Laptop MacBook Air - 2 Nos. 3. NVIDIA Jetson TX1 Development Board - 1 No. 4. Printer HP Laserjet - 1 No. 5. ODROID Boards ( Exynos SoC) - 2 Nos. 6. Smartpower. -1 No. 7. Texas Instruments DSP Board - Indented Facilities : 1. New lab called Systems Lab was created at IIITA under the aegis of the IMPRINT Project. 2. New graduate level elective courses have been offered by the lab with the aim to train students who would serve as the manpower in the project. 3. An IoT/Embedded system has been developed with the intention of validating the power aware compiler under such systems.