Scope and Objectives

We propose to develop prototype radar-on-chips, which will result in a lightweight, portable and inexpensive radar systems. The chip(s) will be developed with an industrial partner for a targeted application with significant potential for commercialization.

Deliverables

Academic prototype chips will be fabricated and integrated in a demo-system (PCB) in collaboration with an industrial partner. If the prototype development effort is successful, after trials, a product will be designed and commercialized (> 100 units).

Scientific Output

Fundamental understanding related to integrated circuit implementation of radars.

Results and outcome till date

1. A PCB based FMCW radar in the S-band, using COTS components was designed and tested. This helped us develop the entire design and test framework for the radar-on-chip. This also gave us a lot of insight into the design of an integrated circuit for a radar-on-chip application. 2. An FMCW synthesizer (frac-N) chip in the S-band was designed using a commercial 180-nm technology and tested. It was found to be functional. 3. This design was integrated into a full S-Band radar transceiver with 1-TX and 3-RX

Societal benefit and impact anticipated

Useful to India's security needs.

Next steps

Can be shared with IMPRINT privately.

Publications and reports

1. V. Jain, S. K. Gupta, V. Khatri and G. Banerjee, "A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications", IEEE Int. Conf. on VLSI Design, New Delhi, India, Jan. 2019.

2. Shravankumar M, Manas Lenka and Gaurab Banerjee, "Integrated Wideband Frequency-hopping Radar System for See-through-wall Sensor Application", International Radio and Microwave Conference, Mumbai, Dec. 2019 (Accepted).

Patents

Scholars and Project Staff

The following project staff are currently employed by this project:
1. Sumit Kumar, Project Associate, Jul. 2018-Present.
2. Rituraj Kar, Project Associate, Feb. 2019-Present.
3. Radhika K, Project Assistant, Jan. 2018-Present.

The following research scholars are attached to the project. Their salaries are not paid by this project:
1. Pushtivardhan Soni, Ph.D. student
2. Shravankumar M, Ph.D. student

Challenges faced

None. Project making tangible progress.

Other information

Silicon fabrication has long lead times. If things proceed on schedule, the time taken from submission of design database to silicon testing is 6-months. This has become 9 months in our case due to fab/assembly delays. Unfortunately, we have no control over manufacturing delays. Testing will start in November 2019 and finish by January 2020. If another revision of this chip is needed, we will not have enough time by the end of the project in August 2020. Hence, the PI requests a 12 month extension to the project with NO COST OVERRUN. However, some re-appropriation of existing allocations will be necessary, for which a request will be sent to IMPRINT.