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Proposal Number: 5360

Domain: Nano-Technology Hardware

Theme(s): Methodology for implementation
Pedagogy
Security

Supporting Central Government Agency: Department of Science and Technology

Budget (Rs. Lakhs): 298.30

Principal Investigator: Dr. Mayank Shrivastava

Principal Investigator Institute: Indian Institute of Science Bangalore

Co-Investigators:

Domain: Nano-Technology Hardware

Project Title

High voltage & ESD device development & enablement for SCL 180nm CMOS Technology

Web Abstract

Drain extended MOS (DeMOS / LDMOS) and ESD protection devices are the key enablers of advance ASICs or System on Chips (SoCs), which allows systems scaling for a range of commercial and strategic products. LDMOS devices enable high voltage circuit operation over the same chip, whereas ESD devices protect ICs from unwanted ESD related failure. SCL’s mandate to feed to the SoC needs of ISRO and other strategic sectors is largely hindered due to unavailability of LDMOS and ESD devices in SCL’s CMOS line. Through this collaborative project IISc will develop 6 different DeMOS devices for integrated high voltage circuit applications, 2 ESD protection devices and will enable it in SCL’s 180nm CMOS line. Device design, simulation, characterization, reliability and device enablement will be taken care by IISc, whereas SCL’s role is to run process lots as per the process/mask details and detailed design of experiments developed by IISc.